System Clock - Xilinx ZC702 User Manual

Table 1-12 lists the pin-to-pin connections from each clock source to the XC7Z020 SoC.
Table 1-12: Clock Connections, Source to XC7Z020 SoC
Clock Reference
U43
U28
U65

System Clock

[Figure 1-2, callout 7]
The system clock source is an LVDS 200 MHz oscillator at U43. It is wired to a multi-region
clock capable (MRCC) input on programmable logic (PL) bank 35. The signal pair is named
SYSCLK_P and SYSCLK_N and each signal is connected to U1 pins D18 and C19 respectively
on the XC7Z020 SoC.
• Oscillator: SiTime SiT9102AI-243N25E200.00000 (200 MHz)
• Frequency Tolerance: 50 ppm
• Differential Output
For more details, see the SiTime SiT9102 data sheet
shown in Figure
X-Ref Target - Figure 1-11
C71
0.1 μF 10V
X5R
ZC702 Board User Guide
UG850 (v1.7) March 27, 2019
Pin Net Name
5 SYSCLK_N
4 SYSCLK_P
5 USRCLK_N
4 USRCLK_P
3 PS_CLK
1-11.
U43
SIT9102
200 MHz
Oscillator
1
OE VCC
2
NC OUT_B
3
GND OUT
GND
Figure 1-11: System Clock Source
www.xilinx.com
I/O Standard XC7Z020 (U1) Pin
LVDS_25
LVDS_25
LVDS_25
LVDS_25
NA
[Ref 18]. The system clock circuit is
VCC2V5
6
R168
5
100Ω 1%
4
Feature Descriptions
C19
D18
Y8
Y9
F7 (Bank 500)
SYSCLK_N
SYSCLK_P
UG850_c1_11_030513
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