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Table 3-7: VCU118 Clock Sources to XCVU9P FPGA U1 Connections (Cont'd)
Clock Source
Device/U#.Pin#
SMA/J35.1
SMA/U38.4
SMA/U38.5
ICS85411A/U21.1
ICS85411A/U21.2
ICS85411A/U21.3
ICS85411A/U21.4
Notes:
1. Series capacitor coupled, MGT connections I/O standard is not applicable.
2. SI570 U32 SI570_OUTPUT_P/N nets are wired to quad clock buffer U104, (1) also applies.
System Clock
[Figure
2-1, callout 11]
The system clock source is a Silicon Labs SI5335A quad clock generator U122. The system
clock (SYSCLK) is a LVDS 300 MHz clock sourced from the CLK0A output pair of U122.
SYSCLK is wired to SI53340 U157 clock MUX/quad-buffer input CLK0 P/N inputs (pins 6 (P)
and 7 (N)).
The 3.3V SI53340 U157 has four LVDS output clock pairs:
•
U157 output Q0 drives clock pair SYSCLK1_300_P/N, connected to XCVU9P FPGA U1
bank 47 global clock (GC) pins G31 and F31 (series capacitor coupled), respectively.
•
U157 output Q1 drives clock pair SYSCLK2_300_P/N which is not connected to XCVU9P
FPGA U1, it is wired to the SI53340 U104 CLK1 input.
•
U157 output Q2 drives clock pair USER_SI570_CLOCK1_P/N, connected to XCVU9P
FPGA U1 bank 64 global clock (GC) pins AW23 and AW22, respectively.
•
U157 output Q3 is not connected.
Clock generator: U122 Silicon Labs SI5335A-B03426-GM (CLK0A 300 MHz)
•
Low phase jitter of 0.7 pS RMS
•
LVDS differential output
•
Quad clock buffer: Silicon Labs SI53340-B-GM (SYSCLK1, SYSCLK2 300 MHz)
•
Additive phase jitter of 43 fs RMS
•
LVDS differential output
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Schematic Net Name
USER_SMA_CLOCK_N
QSFP_SI570_CLOCK_P
QSFP_SI570_CLOCK_N
250MHZ_CLK1_P
250MHZ_CLK1_N
250MHZ_CLK2_P
250MHZ_CLK2_N
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Chapter 3: Board Component Descriptions
I/O Standard
LVDS
(2)
NA
(2)
NA
LVDS
LVDS
LVDS
LVDS
Send Feedback
FPGA (U1) Pin
P32
W9
W8
E12
D12
AW26
AW27
43
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