I/O Voltage Rails; Ddr3 Component Memory; Component Memory Details - Xilinx ZC702 User Manual

I/O Voltage Rails

There are four PL I/O banks available on the XC7Z020 SoC. The voltages applied to the
XC7Z020 SoC I/O banks used by the ZC702 board are listed in
Table 1-3: I/O Voltage Rails
XC7Z020 (U1)
Bank
PL Bank 0
PL Bank 13
PL Bank 33
PL Bank 34
PL Bank 35
PS Bank 500
PS Bank 501
PS Bank 502
Notes:
1. The ZC702 board is shipped with V

DDR3 Component Memory

[Figure 1-2, callout 2]
The 1 GB, 32-bit wide DDR3 memory system is comprised of four SDRAMs at U66–U69. This
memory system is connected to the XC7Z020 SoC processing system (PS) memory interface
bank 502.

Component Memory Details

• Part number: MT41J256M8HX-15E (Micron Technology)
• Configuration: 2Gb: 256 Mb x 8
• Supply voltage: 1.5V
• Datapath width: 32 bits
• Data rate: Up to 1,333 MT/s
The ZC702 XC7Z020 SoC PS DDR bank 502 interface performance is documented in the
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020): DC and AC
Switching Characteristics (DS187) data sheet
The DDR3 0.75V V
The connections between the DDR3 component memory and XC7Z045 SoC bank 502 are
listed in Table
ZC702 Board User Guide
UG850 (v1.7) March 27, 2019
Net Name Voltage
VCC2V5_PL
(1)
VADJ
VCCMIO_PS
VCC1V5_PS
set to 2.5V.
ADJ
termination voltage is sourced from linear regulator U22.
TT
1-4.
www.xilinx.com
2.5V SoC Configuration Bank 0
FMC2, GPIO, PL_PJTAG, IIC_MAIN
FMC2, HDMI Codec
2.5V
FMC1, HDMI Codec
FMC1, HDMI Codec, XADC_GPIO, GPIO
Quad-SPI flash memory, misc
1.8V
Ethernet PHY, USB ULPI Transceiver, SDIO, CAN
1.5V PS_DDR3 MEM
[Ref 3].
Feature Descriptions
Table 1-3.
Connected To
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