Mb Ddr2 Component Memory - Xilinx SP601 User Manual

Chapter 1: SP601 Evaluation Board
Table 1-2: I/O Voltage Rail of FPGA Banks (Cont'd)
References
See the Xilinx Spartan-6 FPGA documentation for more information at
http://www.xilinx.com/support/documentation/spartan-6.htm.

2. 128 MB DDR2 Component Memory

There are 128 MB of DDR2 memory available on the SP601 board. A 1-Gb Elpida
EDE1116ACBG (84-ball) DDR2 memory component is accessible through Bank 3 of the
LX16 device. The Spartan-6 FPGA hard memory controller is used for data transfer across
the DDR2 memory interface's 16-bit data path using SSTL18 signaling. The maximum data
rate supported is 800 Mb/s with a memory clock running at 400 MHz. Signal integrity is
maintained through DDR2 resistor terminations and memory on-die terminations (ODT),
as shown in
Table 1-3: Termination Resistor Requirements
Notes:
1. Nominal value of V
Table 1-4: FPGA On-Chip (OCT) Termination External Resistor Requirements
14
FPGA Bank
2
3
Table 1-3 and
Signal Name
DDR2_A[14:0]
DDR2_BA[2:0]
DDR2_RAS_N
DDR2_CAS_N
DDR2_WE_N
DDR2_CS_N
DDR2_CKE
DDR2_ODT
DDR2_DQ[15:0]
DDR2_UDQS[P,N],
DDR2_LDQS[P,N]
DDR2_UDM, DDR2_LDM
DDR2_CK[P,N]
for DDR2 interface is 0.9V.
TT
FPGA U1 Pin
ZIO
RZQ
www.xilinx.com
I/O Voltage Rail
2.5V
1.8V
Table 1-4.
Board Termination
49.9 ohms to V
TT
49.9 ohms to V
TT
49.9 ohms to V
TT
49.9 ohms to V
TT
49.9 ohms to V
TT
100 ohms to GND
4.7K ohms to GND
4.7K ohms to GND
100 ohm differential at
memory component
FPGA Pin Number
L6
C2
On-Die Termination
ODT
ODT
ODT
Board Connection for OCT
No Connect
100 ohms to GROUND
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009