Ddr4 Component Memory - Xilinx ZCU102 User Manual

Table 3-3: DDR4 SODIMM Socket J1 Connections to FPGA PS DDR Bank 504 (Cont'd)
XCZU9EG
(U1) Pin
AN28 DDR4_SODIMM_CS0_B
AL30
DDR4_SODIMM_CS1_B
The ZCU102 DDR4 SODIMM interface adheres to the constraints guidelines documented in
the PCB Guidelines for DDR4 section of UltraScale Architecture PCB Design Guide (UG583)
[Ref 3] The ZCU102 DDR4 SODIMM interface is a 40Ω impedance implementation. Other
memory interface details are also available in the UltraScale Architecture FPGAs Memory
Interface Solutions Guide (PG150)

DDR4 Component Memory

[Figure 2-1, callout 3]
The 4 Gb, 16-bit wide DDR4 memory system is comprised of one 256 Mb x 16 SDRAM
(Micron MT40A256M16GE-075E) at U2. This memory system is connected to the PL-side
XCZU9EG bank 64. The DDR4 0.6V VTT termination voltage is supplied from sink-source
regulator U35. The connections between the DDR4 memory and XCZU9EG bank 64 are
listed in Table
Table 3-4: DDR4 Component Memory Connection to the XCZU9EG MPSoC
XCZU9EG
(U1) Pin
AM8
AM9
AP8
AN8
AK10
AJ10
AP9
AN9
AP10
AP11
AM10
AL10
AM11
AL11
AK12
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
Net Name
[Ref
3-4.
Net Name I/O Standard
DDR4_A0 SSTL12_DCI
DDR4_A1 SSTL12_DCI
DDR4_A2 SSTL12_DCI
DDR4_A3 SSTL12_DCI
DDR4_A4 SSTL12_DCI
DDR4_A5 SSTL12_DCI
DDR4_A6 SSTL12_DCI
DDR4_A7 SSTL12_DCI
DDR4_A8 SSTL12_DCI
DDR4_A9 SSTL12_DCI
DDR4_A10 SSTL12_DCI
DDR4_A11 SSTL12_DCI
DDR4_A12 SSTL12_DCI
DDR4_A13 SSTL12_DCI
DDR4_BA0 SSTL12_DCI
www.xilinx.com
Chapter 3:
DDR4 SODIMM Memory J1
Pin Number Pin Name
149 CS0_N
157 CS1_N
4].
DDR4 Component Memory
Pin Number
P3
P7
R3
N7
N3
P8
P2
R8
R2
R7
M3
T2
M7
T8
N2
Board Component Descriptions
Pin Name
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC_B
A13
BA0
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