Ddr4 Component Memory - Xilinx ZCU106 User Manual

Table 3-3: DDR4 SODIMM Socket J1 Connections to FPGA PS DDR Bank 504 (Cont'd)
XCZU7EV (U1) Pin
AP33
AK32
The ZCU106 DDR4 SODIMM interface adheres to the constraints guidelines documented in
the "PCB Guidelines for DDR4" section of the UltraScale Architecture PCB Design Guide
(UG583) [Ref 3]. The DDR4 SODIMM interface is a 40Ω impedance implementation. Other
memory interface details are also available in the UltraScale Architecture FPGAs Memory
Interface Solutions Guide (PG150)

DDR4 Component Memory

[Figure 2-1, callout 2]
The 2 GB 64-bit wide DDR4 memory system is comprised of four 256 Mb x 16 SDRAMs
(Micron MT40A256M16GE-075E) U2 and 99–101. This memory system is connected to
PL-side XCZU7EV banks 64, 65, and 66. The DDR4 0.6V VTT termination voltage is supplied
from sink-source regulator U35. The connections between the DDR4 memory and the
XCZU7EV device are listed in
Table 3-4: DDR4 Component Memory Connection to the XCZU7EV MPSoC
XCZU7EV
Net Name
(U1) Pin
AF16 DDR4_DQ0
AF18 DDR4_DQ1
AG15 DDR4_DQ2
AF17 DDR4_DQ3
AF15 DDR4_DQ4
AG18 DDR4_DQ5
AG14 DDR4_DQ6
AE17 DDR4_DQ7
AA14 DDR4_DQ8
AC16 DDR4_DQ9
AB15 DDR4_DQ10
AD16 DDR4_DQ11
AB16 DDR4_DQ12
AC17 DDR4_DQ13
AB14 DDR4_DQ14
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
Net Name
DDR4_SODIMM_CS0_B
DDR4_SODIMM_CS1_B
[Ref 4].
Table 3-4.
I/O Standard
Pin #
POD12_DCI G2
POD12_DCI F7
POD12_DCI H3
POD12_DCI H7
POD12_DCI H2
POD12_DCI H8
POD12_DCI
POD12_DCI
POD12_DCI A3
POD12_DCI B8
POD12_DCI C3
POD12_DCI C7
POD12_DCI C2
POD12_DCI C8
POD12_DCI D3
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Chapter 3: Board Component Descriptions
DDR4 SODIMM Memory J1
Pin Number
149
157
DDR4 Component Memory
Pin Name
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
J3 DQL6
J7 DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
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Pin Name
CS0_N
CS1_N
Ref. Des.
U101
U101
U101
U101
U101
U101
U101
U101
U101
U101
U101
U101
U101
U101
U101
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