Pl-Side: Ddr4 Component Memory - Xilinx ZCU111 User Manual

The ZCU111 XCZU28DR RFSoC PS DDR interface maximum 2133 MT/s performance is
documented in the Zynq UltraScale+ RFSoC Data Sheet
The ZCU111 DDR4 SODIMM interface adheres to the constraints guidelines documented in
the PCB guidelines for DDR4 section of the UltraScale Architecture PCB Design User Guide
(UG583) [Ref 4]. The DDR4 SODIMM interface is a 40Ω impedance implementation. Other
memory interface details are also available in the UltraScale Architecture-Based FPGAs
Memory IP LogiCORE IP Product Guide (PG150)
MTA4ATF51264HZ-2G6E1 data sheet at the Micron website
The connections between the DDR4 SODIMM socket J50 and XCZU28DR PS bank 504 are
referenced in Appendix B, Xilinx Design

PL-Side: DDR4 Component Memory

[Figure 2-1, callout 3]
The 4 GB, 64-bit wide DDR4 memory system is comprised of four 512 Mb x 16 SDRAM, U80
and U94-U96.
• Manufacturer: Micron
• Part Number: MT40A512M16JY-075E
• Description:
8 Gb (512 Mb x 16)
°
1.2V 96-ball TFBGA
°
DDR4-2666
°
This memory system is connected to PL-side XCZU28DR banks 67, 68, and 69. The DDR4
0.6V VTT termination voltage is supplied from sink-source regulator U81.
The ZCU111 board DDR4 64-bit component memory interface adheres to the constraints
guidelines documented in the PCB guidelines for DDR4 section of UltraScale Architecture
PCB Design User Guide (UG583)
impedance implementation. Other memory interface details are also available in the
UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150)
For more details, see the Micron MTA4ATF51264HZ-2G6E1 data sheet at the Micron website
[Ref 15]
The connections between the DDR4 component memories and the XCZU28DR banks are
referenced in Appendix B, Xilinx Design
ZCU111 Board User Guide
UG1271 (v1.1) August 6, 2018
Chapter 3: Board Component Descriptions
[Ref 5]. For more details, see the Micron
Constraints.
[Ref 4]. The ZCU111 DDR4 component interface is a 40Ω
Constraints.
www.xilinx.com
(DS926)[Ref 2].
[Ref 15].
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[Ref 5].
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