Operation Of Port 0 - Fujitsu F2MC-8L Series Hardware Manual
8-bit microcontroller
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Also See for F2MC-8L Series:
- Hardware manual (131 pages) ,
- Application note (14 pages) ,
- Getting started (15 pages)
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4.2.2
Operation of Port 0
This section describes the operation of the port 0.
Operation of Port 0
Operation as an output port
•
Setting the corresponding DDR0 register bit to "1" sets a pin as an output port.
•
When a pin is set as an output port, the output buffer is "ON" and the pin outputs the data
stored in the output latch.
•
Writing data to the PDR0 register stores the data in the output latch and outputs the data to
the pin through the output buffer.
•
Reading the PDR0 register returns the pin value.
Operation as an input port
•
Setting the corresponding DDR0 register bit to "0" sets a pin as an input port.
•
When a pin is set as an input port, the output buffer is "OFF" and the pin goes to the high-
impedance state.
•
Writing data to the PDR0 register stores the data in the output latch but does not output the
data to the pin.
•
Reading the PDR0 register returns the pin value.
Operation for external interrupt input (MB89120A series only)
•
Setting the bit in the DDR0 register to "0", which corresponds to an external interrupt input
pin, sets the pin as an input port pin.
•
Whether external interrupt input and interrupt request output have been enabled or disabled,
the pin value can be obtained by reading the PDR0 register.
Operation at reset
•
Resetting the CPU initializes the DDR0 register values to "0". This sets all output buffers to
"OFF" (all pins become input ports) and sets the pins to the high-impedance state.
•
The PDR0 register is not initialized by a reset. Therefore, to use as output ports, the output
data must be set in the PDR0 register before setting the corresponding DDR0 register bits to
output.
Operation in stop mode or watch mode
The pins go to the high-impedance state if the pin state specification bit in the standby control
register (STBC: SPL) is "1" when the device changes to stop or watch mode. This is achieved
by forcibly setting the output buffer to "OFF" regardless of the DDR0 register values. Note that,
on the MB89121 and MB89P131, the input is fixed to prevent leakage by opening the input.
On the MB89120A series, the input is not fixed to input external interrupts. Pins which are not
used for external interrupts must be set to "0" or "1".
4.2 Port 0
105
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