Figure 4.2 Block Diagram Of Port 0 And 1 Pin (Single-Chip Mode); Table 4.2B Correspondence Between Pin And Register For Port 0 And Port 1 - Fujitsu F2MC-8L MB89620 Series Hardware Manual

n Block Diagram of Port 0 and 1 Pin (Single-chip Mode)
SPL: Pin state specification bit in the standby control register (STBC)
n Port 0 and 1 Registers
The port 0 registers consist of PDR0 and DDR0. The port 1 registers consist of PDR1 and
DDR1. However, accessing these registers in external bus mode has no meaning.
Each bit in these registers has a one-to-one relationship with a port 0 and 1 pin respectively.
Table 4.2b shows the correspondence between pins and registers for ports 0 and 1.
Table 4.2b Correspondence
Port
Port 0
Port 1
MB89620 series
PDR (Port data register)
PDR read
PDR read (for bit manipulation instructions)
Output latch
PDR write
DDR
DDR write (Port data direction register)

Figure 4.2 Block Diagram of Port 0 and 1 Pin (Single-chip Mode)

between
Correspondence between register bit and pin
PDR0, DDR0
Corresponding pin
PDR1, DDR1
Corresponding pin
Input buffer
Output buffer
Stop mode (SPL=1)
Pin and Register for Ports 0 and 1
Bit 7 Bit 6 Bit 5 Bit 4
P07 P06 P05 P04
Bit 7 Bit 6 Bit 5 Bit 4
P17 P16 P15 P14
Pull-up resistor
(optional)
Approx. 50 kΩ/5.0 V
Pin
Bit 3 Bit 2 Bit 1
P03 P02 P01
Bit 3 Bit 2 Bit 1
P13 P12 P11
CHAPTER 4 I/O PORTS
Bit 0
P00
Bit 0
P10
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