Refresh Timing (Sdram Access) - Renesas PFESiP/V850EP1 User Manual

32-bit microcontroller dedicated to pfesip ep-1
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(c) Refresh Timing (SDRAM access)
TRPW
BUSCLK
(output)
A0-A25
(output)
< t
DKREF
REFRQZ
(output)
Note
CSZn
(output)
SDRASZ
(output)
SDCASZ
(output)
SDWEZ
(output)
DQM0-DQM3
H
(output)
SDCKE
H
(output)
Note
n = 1, 3, 4, 6
CHAPTER 1 PRODUCT SPECIFCATIONS
Figure 1-11. Refresh Timing (SDRAM Access)
ALLPRE
REFW
REFW
< t
>
< t
>
DKA
DKA
>
< t
>
< t
>
DKCS
DKCS
< t
> < t
>
DKRAS
DKRAS
< t
>
< t
>
DKWE
DKWE
User's Manual A19069EJ2V0UM
REFW
TREF
REFW
< t
>
< t
>
DKCS
DKCS
< t
> < t
>
DKRAS
DKRAS
< t
>
< t
>
DKCAS
DKCAS
TRPW
TRPW
TRPW
< t
>
DKREF
29

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