Related Manuals for Broadcom NetXtreme/NetLink BCM5719
Summarization of Contents
About This Document
Purpose and Audience
Outlines the document's scope, target audience, and related information for NetXtreme/NetLink controllers.
Document Conventions
Describes formatting and typographical conventions used throughout the document.
Section 4: Common Data Structures
Descriptor Rings
Describes shared buffer descriptor (BD) rings used for host-controller communication.
Section 5: Receive Data Flow
Receive Producer Ring
Explains the host-based ring that points to empty host receive buffers for packet data.
Section 6: Transmit Data Flow
Send Rings
Covers shared data structures for describing data buffers to be transferred onto the network.
Section 7: Device Control
Initialization Procedure
Provides a step-by-step guide for the MAC initialization process.
Section 8: IEEE1588
NetXtreme Time Sync Assist
Describes hardware features assisting IEEE1588 and IEEE802.1AS traffic.
Section 9: PCI
Configuration Space
Describes the PCI configuration space, its regions, and registers.
Power Management
Details the power management capabilities and ACPI states supported by the Ethernet controller.
Section 10: Ethernet Link Configuration
GMII/MII
Describes the Gigabit Media Independent Interface and Media Independent Interface.
PHY Control
Details the control of the physical layer interfaces.
Section 11: Interrupt Processing
NetXtreme Legacy Interrupt Model
Reviews the legacy interrupt model for NetXtreme controllers.
Basic Driver Interrupt Processing Flow
Details the standard driver interrupt service routine flow.
Host Coalescing
Description
Explains the concept of host coalescing for performance.
Registers
Lists registers related to status block updates and interrupt generation.
Section 12: IO Virtualization (IOV)
Data Structure and Register Changes for IOV
Details changes to data structures and registers to support IOV.
IOV – Receive Side
Describes the receive-side solutions for IOV acceleration.
IOV – Transmit Side
Discusses transmit enhancements for IOV.
Section 13: Ethernet Controller Register Definitions
BCM5718 Family Register MAP
Shows the internal register map for the BCM5718 family.
PCI Configuration Registers
Details the PCI configuration registers used by the Ethernet controller.
Device ID and Vendor ID Register (offset: 0x00)
Identifies the device and vendor IDs.
Status and Command Register (offset: 0x04)
Controls device status and command functions.
Power Management Control/Status Register (offset: 0x4C)
Controls and reports power management status.
MSI Capability Header (offset: 0x58)
Provides header information for Message Signaled Interrupts.
Advanced Error Reporting Enhanced Capability Header (offset: 0x100)
Details enhanced capability headers for advanced error reporting.
Uncorrectable Error Status Register (offset: 0x104)
Reports the status of uncorrectable errors.
Correctable Error Status Register (offset: 0x110)
Reports the status of correctable errors.
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