Rom/Prom/Eprom/Eeprom Cycle Times - Motorola MVME135 User Manual

I
FUNCTIONAL DESCRIPTION
The addition of the PMMU adds one wait cycle (three minimum
+
one
wait cycle). Parity adds one wait cycle to the total number of MPU
clock cycles, (four total for the MVME135/135-1 and five total for
the MVME136).
4.2.5 MVMEl35A/136A DRAM Cycle Times
MPU accesses to the on-board DRAM require four MPU clock cycles
(three minimum + one wait cycle) for slower memories. A clock cycle
at 16.67 MHz is 60 nanoseconds.
The addition of a PMMU adds one wait cycle (three minimum + one wait
cycle). Parity does not add additional wait cycles on the
MVME135A/136A.
TABLE 4-1. MVME135/136 TIMING
MVME135
MVME135'1
MVME135A MVMEl36
MVME136A
ACCESS SEQUENCE
(15.67 MHz) (20.00 101Hz) (16.57 101Hz) (16.57 MHz) (16.67 101Hz)
WRITE READ
WRITE
READ WRITE READ WRITE READ WRITE READ
MPU TO LOCAL DRAM 3 3 3 3 4 4
4
4 5 5
(NO PARITY)
MPU TO LOCAL DRAM
4 4
4 4 4 4
5 5
5 5
(PARITY ENABLED)
MPU TO LOCAL ROM /
..
B
..
B
..
9
..
9
..
9
PROM/EPROM
VMEbua TO LOCAL
11
10 11 11 11 10 12 11 12 11
DRAM
MPU TO GLOBAL DRAM
OVER VSB B B 9 9 B B 9 9 9
9
(MVME204 • 2F )
MPU TO GLOBAL DRAM
OVER VMEbua 9 10 12 14 9 10
10 11
10 11
(MVME204 • 2F )
WRITE READ WRITE READ WRITE READ WRITE READ WRITE
READ
ACCESS SEOUENCE
MVME135 MVMEI3S·1 MVMEI3SA MVME135 MVME136A
(16.67 101Hz) (20.00 101Hz) (16.67 101Hz)
(16.67 101Hz)
(16.67 101Hz)
ALL T1MES ARE TOTAL NUMBER OF MC6B020 CLOCK CYCLES.
4.2.6 ROM/PROM/EPROM/EEPROM Cycle Tines
All ROM/PROM/EPROM/EEPROM accesses require eight MPU clock cycles
when NO PMMU is installed, and nine MPU clock cycles to complete when
the PMMU is installed.
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