Figure 19-6 Dram Read Cycle 16-Bit Access (Cpu Bus Master) Timing Diagram; Table 19-8 Dram Read Cycle 16-Bit Access (Cpu Bus Master) Timing Parameters - Motorola MC68VZ328 User Manual

MD[12:0]
1
RASx
CASx
DWE
OE
D[15:0]
Figure 19-6. DRAM Read Cycle 16-Bit Access (CPU Bus Master) Timing Diagram
Table 19-8. DRAM Read Cycle 16-Bit Access (CPU Bus Master) Timing Parameters
Number
1 Row address valid to RASx asserted
2 DWE negated before row address valid
3 OE asserted before RASx is asserted
4 RASx asserted before row address invalid
(MSW = 0,1)
5 Column address valid to CASx asserted
(MSW = 0,1)
6 RASx asserted to CASx asserted
(MSW = 0,1)
7 RASx pulse width (SLW = 0,1)
8 CASx pulse width (BC[1:0] = 00,01,10,11)
9 CASx asserted to data-in valid
(BC[1:0] = 00,01,10,11 for FPM)
10 Data-in hold after CASx is negated
11 OE negated after CASx is negated
Row
4
6
2
3
9
Characteristic
Electrical Characteristics
AC Electrical Characteristics
Column
12
5
8 13
7
11
10
(3.0 ± 0.3) V
Minimum
40
0
0
12,27
10,25
28,58
90,120
28,58,88,118
— 15,45,75,105 (FPM)
0 (FPM)
30 (EDO)
0 (FPM)
30 (EDO)
Row
14
Unit
Maximum
— ns
— ns
— ns
— ns
— ns
32 ns
— ns
— ns
ns
20 (EDO)
— ns
35 ns
19-9