External Bus Interface Unit; Ebiu Overview - Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual

6 EXTERNAL BUS INTERFACE
UNIT
The External Bus Interface Unit (EBIU) provides glueless interfaces to
external memories. The processor supports Synchronous DRAM
(SDRAM) including mobile SDRAM, and is compliant with the PC100
and PC133 SDRAM standards. The EBIU also supports asynchronous
interfaces such as SRAM, ROM, FIFOs, flash memory, and ASIC/FPGA
designs.

EBIU Overview

The EBIU services requests for external memory from the core or from a
DMA channel. The priority of the requests is determined by the external
bus controller. The address of the request determines whether the request
is serviced by the EBIU SDRAM controller or the EBIU asynchronous
memory controller.
The DMA controller provides high-bandwidth data movement capability.
The Memory DMA (MDMA) channels can perform block transfers of
code or data between the internal memory and the external memory
spaces. The MDMA channels also feature a Handshake Operation mode
(HMDMA) via dual external DMA request pins. When used in conjunc-
tion with the EBIU, this functionality can be used to interface high-speed
external devices, such as FIFOs and USB 2.0 controllers, in an automatic
manner. For more information on HMDMA and the external DMA
request pins, please refer to
ADSP-BF537 Blackfin Processor Hardware Reference
Chapter 5, "Direct Memory Access".
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