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(3) Automatic data transmit/receive control register (ADTC)
This register sets automatic receive enable/disable, the operating mode, strobe output enable/disable, busy
input enable/disable, and error check enable/disable, and displays automatic transmit/receive execution and
error detection.
ADTC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets ADTC to 00H.
Figure 19-4. Automatic Data Transmit/Receive Control Register Format
Symbol
<7>
<6>
ADTC
RE
ARLD ERCE ERR
Notes 1. Bits 3 and 4 (TRF and ERR) are read-only bits.
2. The termination of automatic transmission/reception should be judged by using TRF, not CSIIF1
(interrupt request flag).
Caution When an external clock input is selected with bit 1 (CSIM11) of the serial operating mode
register 1 (CSIM1) set to 0, set STRB and BUSY1 of ADTC to 0, 0.
Remark x: Don't care
420
CHAPTER 19 SERIAL INTERFACE CHANNEL 1
<5>
<4>
<3>
<2>
<1>
TRF STRB
BUSY1 BUSY0
R/W
BUSY1
R/W
STRB
R
R
R/W
ERCE
R/W
ARLD
R/W
<0>
Address
After Reset
R/W
FF69H
00H
R/W
BUSY0
Busy Input Control
0
x
Not using busy input
1
0
Busy input enable (active high)
1
1
Busy input enable (active low)
Strobe Output Control
0
Strobe output disable
1
Strobe output enable
TRF
Status in Automatic Transmit/Receive Function
Detection of termination of automatic transmission/
0
reception (This bit is set to 0 upon suspension of
automatic transmission/reception or when ARLD = 0.)
During automatic transmission/reception
1
(This bit is set to 1 when data is written to SIO1.)
ERR
Error Detection in Automatic Transmit/Receive Function
No error (Set to 0 when data is written to SIO1)
0
1
Error occurred
Error Check in Automatic Transmit/Receive Function
0
Error check disable
Error check enable (only when BUSY1 = 1)
1
Operating Mode for Automatic Transmit/Receive Function
0
Single operating mode
1
Repetitive operating mode
RE
Receive operation in Automatic Transmit/Receive Function
0
Receive disable
1
Receive enable
Note 1
Note 2
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