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3.3.15 Questionable event status register
This is a register that reports abnormal status of the instrument. It is readable by
:STATus:QUETionable[:EVENt]? query. After reading or by CLS command, the register is cleared to
0.
This register maintains status change until it is cleared. This is used for obtaining SRQ occurrence
factor. In order to obtain a latest abnormal status, please use questionable condition status register.
This register is 16 bit configuration and the description is as follows:
(Bit 15)
This instrument does not use this bit.
This bit is normally set at "0".
OVM (Bit 14)
Since a storage number exceeds the set number due to FIFO storage of LOG, it
becomes 1 in the case data from beginning is destroyed.
(Bit 13)
This instrument does not use this bit.
This bit is normally set at "0".
Hout (Bit 12)
Becomes 1 in the case limit calculation result is larger than upper limit value.
Lout (Bit 11)
Becomes 1 in the case limit calculation result is smaller than lower limit value.
(Bit 10)
This instrument does not use this bit.
This bit is normally set at "0".
Becomes 1 in the case 2WΩ/4WΩ measurement becomes overload.
OVR (Bit 9)
(Bit 5-8)
This instrument does not use this bit.
This bit is normally set at "0".
OVT(Bit 4)
Becomes 1 in the case TEMP measurement becomes overload.
(Bit 2-3)
This instrument does not use this bit.
This bit is normally set at "0".
OVC (Bit 1)
Becomes 1 in the case DCI/ACI measurement becomes overload.
OVV (Bit 0)
Becomes 1 in the case DCV/ACV measurement becomes overload.
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