Standard Event Status Register - Iwatsu VOAC760 Manual

3.3.4

Standard event status register

This register can be read using the  ESR? query. After the contents of this register are masked by the
standard event status enable register, the logical sum of all bits is connected to the ESB bit of the
status byte register.
The contents of this register are cleared (that is, set to 0) when the register is read using the  CLS
command or  ESR? query.
This register consists of 8 bits, and each bit has the following contents.
PON (Bit 7)
(Bit 6)
CME (Bit 5)
EXE (Bit 4)
DDE (Bit 3)
QYE (Bit 2)
(Bit 1)
OPC (Bit 0)
After the power is turned on, this bit is set to 1.
This instrument does not use bit 6. Bit 6 is always set to 0.
If a command error occurs, this bit is set to 1.
This indication shows that some error exists in the command syntax.
If the execution error is given, this bit is set to 1. This indication shows that the
command cannot be executed or could not be completely normally.
If an instrument-specific error occurs, this bit is set to 1.
This is a summary message of the DDER register.
If a query error occurs, this bit is set to 1.
This indication shows that an error occurs when the controller attempts to read the
message from this instrument without sending the query command, or the next
message is sent before the response message has not been completely read.
This instrument does not use bit 1. Bit 1 is always set to 0.
When the operation is completed, this bit is set to 1. This bit supports the
 OPC-command-based controller-instrument synchronization.
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