Table of Contents
Advertisement
3.3.7
Instrument specific error occurrence event status register
This is a register that reports abnormal status of the instrument. It is readable by :DDER? Query.
After reading, the register is cleared to 0.
In CLS command, the register is cleared to 0 at the time of power-up.
This register is 8 bit configuration and the description is as follows:
SPE (Bit 7)
Indicates parity error occurrence in serial interface.
SFE (Bit 6)
Indicates framing error in serial interface.
SOE (Bit 5)
Indicates overrun error in serial interface.
(Bit 4)
This instrument does not use this bit.
This bit is normally set at "0".
HLE (Bit 3)
Indicates upper and lower limit value setting error (H<L) of limit operation.
(Bit 2)
This instrument does not use this bit.
This bit is normally set at "0".
OVM (Bit 1)
Shows that the scaling calculation result over scaling occurs.
(Bit 0)
This instrument does not use this bit.
This bit is normally set at "0".
29
Advertisement
Table of Contents
