Questionable Condition Status Register - Iwatsu VOAC760 Manual

3.3.14 Questionable condition status register

This is a register that reports abnormal status of the instrument. It is readable by
:STATus:QUESionable:CONDition? query. There is no change of register value by reading.
This register indicates a latest status. In the case SRQ occurrence factor is obtained, please use the
questionable event status register (and enable register).
This register is 16 bit configuration and the description is as follows:
(Bit 15) This instrument does not use this bit.
This bit is normally set at "0".
FUL(Bit 14) Since a storage number exceeds the set number due to FIFO storage of LOG, it
becomes 1 in the case data from beginning is destroyed.
(Bit 13) This instrument does not use this bit.
This bit is normally set at "0".
Hout (Bit 12) Becomes 1 in the case limit calculation result is larger than upper limit value.
Lout (Bit 11) Becomes 1 in the case limit calculation result is smaller than lower limit value.
(Bit 10) This instrument does not use this bit.
This bit is normally set at "0".
This bit is normally set at "0". Please perform reading by an event status register.
OVR (Bit 9)
(Bit 5-8) This instrument does not use this bit.
This bit is normally set at "0".
This bit is normally set at "0". Please perform reading by an event status register.
OVT (Bit 4)
(Bit 2-3) This instrument does not use this bit.
This bit is normally set at "0".
This bit is normally set at "0". Please perform reading by an event status register.
OVC (Bit 1)
This bit is normally set at "0". Please perform reading by an event status register.
OVV (Bit 0)
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