Table of Contents
Advertisement
3.3.12 Operation event status register
This is a register that reports change of the instrument status. It is readable by
:STATus:OPERation[:EVENt]? query. After reading or by CLS command, the registered is cleared to
0. This register maintains status change until it is cleared. This is used in the case SRQ occurrence
factor is obtained. In the case a latest status is obtained, please use the operation condition status
register.
This register is 16 bit configuration and the description is as follows:
(Bit 6-15)
This instrument does not use this bit.
This bit is normally set at "0".
WTR (Bit 5)
Sets to 1 when measurement is trigger wait status.
MSR (Bit 4)
Becomes 1 during measuring status.
(Bit 0-3)
This instrument does not use this bit.
This bit is normally set at "0".
3.3.13 Operation event enable register
This is a register to mask an operation event status register. Depending upon the masked result,
OPS bit of standard event status register is set.
It is possible to set and read out the mask pattern by :STATus:OPERation:ENABle[?] command.
This register is PSC command and is settable whether it is to be 0 or not at the time of power-up.
It is not affected by instrument clear and CLS command.
Operation event status constitution
0
0
0
0
X
X
X
X
Not used
0
0
0
0
0
X
X
X
X
X
Tigger wait status
Measurement status
5
4
0
WTR MSR
0
0
Operation event status register
AND
AND
Ｘ
X
X
Operation event enable register
OR
To OPS of status byte register
33
Not used
0
0
X
X
X
Advertisement
Table of Contents
