Reference Clock Interface; Lvpecl; Ac Coupled Reference Clock - Xilinx Virtex-6 FPGA User Manual

Reference Clock Interface

This section discusses the interface between an external reference clock and the GTH
transceiver reference clock input. Specifically the interface to an external reference clock
with an LVPECL output including AC coupling, pin connections for unused reference
clock inputs, and signal integrity issues related to the reference clock circuit.

LVPECL

A reference clock oscillator with an LVPECL output is recommended. An LVDS output
reference clock oscillator is not recommended because the LVDS output does not meet the
minimum signal amplitude requirements for the GTH transceiver reference clock input.
Figure 5-5
oscillator to the GTH transceiver reference clock input.
X-Ref Target - Figure 5-5
Figure 5-5: Interfacing an LVPECL Oscillator and GTH Transceiver Reference Clock
Notes relevant to
1.

AC Coupled Reference Clock

AC coupling of the oscillator reference clock output to the GTH Quad reference clock
inputs serves multiple purposes:
•
•
•
To minimize noise and power consumption, external AC coupling capacitors between the
sourcing oscillator and the GTH Quad dedicated clock reference clock input pins are
required.
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
provides an example of how to interface an LVPECL output reference clock
LVPECL Oscillator
Figure 5-5:
The resistor values shown are nominal values. Refer to the oscillator vendor data sheet
for the actual bias resistor requirement.
It blocks DC current between the oscillator and the GTH Quad dedicated clock input
pins. This has the added benefit of reducing the power consumption of both parts.
Common mode voltage independence is achieved.
The AC coupling capacitor forms a high-pass filter with the on-chip termination that
attenuates reference clock wander.
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Internal to
Virtex-6 FPGA
0.1 µF
240Ω
0.1 µF
240Ω
GTH Reference
Clock Input Buffer
Input
Reference Clock
UG371_c5_05_120809
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