Serial Mode Register (Smr); Figure 8.4-2 Serial Mode Register (Smr) - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 8 8-BIT SERIAL I/O
8.4.1

Serial Mode Register (SMR)

The serial mode register (SMR) is used to enable or disable serial I/O operation, select
the shift clock, set the transfer direction, control interrupts, and check the state of 8-bit
serial I/O.
Serial Mode Register (SMR)
Address Bit 7
001C SIOF
H
R/W
R/W : Readable and writable
: Initial value
200

Figure 8.4-2 Serial Mode Register (SMR)

Bit 6 Bit 5 Bit 4 Bit 3
SIOE SCKE SOE CKS1
R/W R/W R/W R/W
Bit 2 Bit 1 Bit 0 Initial value
CKS0 BDS SST 00000000
R/W R/W R/W
Serial I/O transfer start bit
SST
Read
0
Serial transfer stopped.
1
Serial transfer operating.
BDS Transfer direction selection bit
LSB first
0
(starts transfer from the least significant bit)
MSB first
1
(starts transfer from the most significant bit)
CKS1 CKS0 Shift clock selection bits
0 0
0 1
Internal shift clock
1 0
1 1 External shift clock
t : Instruction cycle
inst
SOE Serial data output enable bit
0 Functions P31/SO as a general-purpose port.
1 Functions P31/SO as the serial data output pin.
Shift clock output enable bit
SCKE
Functions P30/SCK as a general-purpose port
0
or shift clock input pin.
Functions P30/SCK as the shift clock output
1
pin.
Interrupt request enable bit
SIOE
0 Disables interrupt request output.
1 Enables interrupt request output.
Interrupt request flag bit
SIOF
Read
0
Transfer has not completed.
1
Transfer has completed.
B
Write
Stops/disables serial transfer.
Starts/enables serial transfer.
SCK
pin
2 t Output
inst
8 t Output
inst
32 t Output
inst
Input
Write
Clears this bit.
No effect. The bit does not
change.