Motorola MPC823e Reference Manual page 866

Communication Processor Module
SMSYNx
SMCLK
SMTXD 1s ARE SENT
TEN
SET
HERE
SMSYNx
SMCLK
SMRXD
REN SET
HERE OR
ENTER
HUNT MODE
COMMAND
ISSUED
NOTES:
1. SMCLK is an internal clock derived from an external clock pin or a baud rate generator.
2. This example shows the SMC receiver and transmitter enabled separately. If the REN
and TEN bits were set at the same time, a single falling edge of SMSYNx would
synchronize both.
Figure 16-120. SMSYNx Pin Synchronization
If both the REN and TEN bits are set in the SMCMR, the first falling edge of the SMSYNx
pin causes both the transmitter and receiver to achieve synchronization. To resynchronize
the transmitter or receiver, the SMCx transmitter/receiver can be disabled and reenabled
and the SMSYNx pin can be used again to resynchronize the transmitter or receiver. Refer
to Section 16.11.5 Disabling the SMCs On-the-Fly for a description of how to safely
disable and reenable a serial management controller. Simply clearing and setting the TEN
bit may not be sufficient.
16-412
FIVE 1s ARE SENT
TX FIFO FIVE 1s
SMSYNx
LOADED ASSUME
DETECTED
APPX. CHARACTER
LOW HERE
HERE LENGTH
EQUALS 5
FIRST BIT OF
SMSYNx
RECEIVE
DETECTED
DATA (LSB)
LOW HERE
MPC823e REFERENCE MANUAL
SMC1 TRANSMIT DATA
FIRST BIT OF TRANSMISSION
FIRST 5-BIT COULD BEGIN
TRANSMIT HERE IF TX FIFO
CHARACTER NOT LOADED IN
(LSB) TIME
SMC1 RECEIVE DATA
MOTOROLA