Table of Contents
Advertisement
Development Capabilities and Interface
PRI—Program Interrupt
This bit is set when the program interrupt is asserted.The core enters in debug mode if
enabled and the PRIE bit in the DER is set.
FPUVI—Floating-Point Unavailable Interrupt
This bit is set when the floating-point unavailable interrupt is asserted. The core enters
debug mode if enabled and the FPUVIE bit in the DER is set.
DECI—Decrementer Interrupt
This bit is set when the decrementer interrupt is asserted. The core enters debug mode if
enabled and the DECIE bit in the DER is set.
Bits 11–12, 15–16—Reserved
These bits are reserved and must be set to 0.
SYSI—System Call Interrupt
This bit is set when the system call interrupt is asserted. The core enters debug mode if
enabled and the SYSIE bit in the DER is set.
TR—Trace Interrupt
This bit is set when in single-step mode or when in branch trace mode. The core enters
debug mode if enabled and the TRE bit in the DER is set.
SEI—Implementation Dependent Software Emulation Interrupt
This bit is set when the floating-point assist interrupt is asserted. The core enters debug
mode if enabled and the SEIE bit in the DER is set.
ITLBMS—Implementation Specific Instruction TLB Miss
This bit is set as a result of an instruction TLB miss.The core enters debug mode if enabled
and the ITLBMSE bit in the DER is set.
DTLBMS—Implementation Specific Data TLB Miss
This bit is set as a result of an data TLB miss. The core enters debug mode if enabled and
the DTLBMSE bit in the DER is set.
ITLBER—Implementation Specific Instruction TLB Error
This bit is set as a result of an instruction TLB error. The core enters debug mode if enabled
and the ITLBERE bit in the DER is set.
DTLBER—Implementation Specific Data TLB Error
This bit is set as a result of an data TLB error. The core enters debug mode if enabled and
the DTLBERE bit in the DER is set.
Bits 22–27—Reserved
These bits are reserved and must be set to 0.
20-56
MPC823e REFERENCE MANUAL
MOTOROLA
Advertisement
Table of Contents
