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MPC823e Instruction Set—lmw
lmw
Assembler Syntax
BIT
0
1
2
FIELD
46
BIT
16
17
18
FIELD
Definition
Operation
Description
B-78
lmw
rD,d(rA)
3
4
5
6
7
19
20
21
22
23
d
Load Multiple Word
if rA = 0 then b ← 0
else b ← (rA)
EA ← b + EXTS(d)
r ← rD
do while r ≤ 31
GPR(r) ← MEM(EA, 4)
r ← r + 1
EA ← EA + 4
EA is the sum (rA|0) + d. n = (32 – rD). n consecutive words
starting at EA are loaded into GPRs rD through r31.
EA must be a multiple of four. If it is not, either the system
alignment exception handler is invoked or the results are
boundedly undefined. If rA is in the range of registers specified
to be loaded, including the case in which rA = 0, the instruction
form is invalid.
Note that, in some implementations, this instruction is likely to
have a greater latency and take longer to execute, perhaps
much longer, than a sequence of individual load or store
instructions that produce the same results.
Other registers altered:
None
POWERPC ARCHITECTURE
LEVEL
UISA
MPC823e REFERENCE MANUAL
8
9
10
11
12
D
24
25
26
27
28
SUPERVISOR
OPTIONAL
LEVEL
13
14
15
A
29
30
31
FORM
D
MOTOROLA
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