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MPC823e Instruction Set—srw
srw
Assembler Syntax
BIT
0
1
2
FIELD
31
BIT
16
17
18
FIELD
B
Definition
Operation
Description
B-126
srw
rA,rS,rB (Rc = 0)
srw.
rA,rS,rB (Rc = 1)
3
4
5
6
7
19
20
21
22
23
Shift Right Word
← rB[27-31]
n
r ← ROTL(rS, 32 –
)
n
The contents of rS are shifted right the number of bits specified
by the low-order six bits of rB. Bits shifted out of position 31 are
lost. Zeros are supplied to the vacated positions on the left. The
result is placed into rA.
Other registers altered:
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO (if Rc = 1)
POWERPC ARCHITECTURE
LEVEL
UISA
MPC823e REFERENCE MANUAL
8
9
10
11
12
S
24
25
26
27
28
536
SUPERVISOR
OPTIONAL
LEVEL
13
14
15
A
29
30
31
RC
FORM
X
MOTOROLA
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