Motorola MPC823e Reference Manual page 963

Communication Processor Module
In a polled interrupt scheme, you must periodically read the CIPR. When a pending interrupt
is handled, clear the corresponding bit in the CIPR. However, if an event register exists,
clear the unmasked event register bits instead, thus causing the CIPR bit to be cleared. To
clear a bit in the CIPR, write a 1 to that bit. Since you can only clear bits in this register, bits
written as zeros are unaffected. The CIPR is cleared at reset.
Note: The USB or SCCx CIPR bit positions are not changed according to the relative
priority between the USB or SCCs (as determined by the SCxP and SPS bits in
the CICR). Writing a zero to a bit in the CIPR has no effect.
16.15.5.3 CPM INTERRUPT MASK REGISTER. Each bit in the 32-bit read/write CPM
interrupt mask register (CIMR) corresponds to a CPM interrupt source. You can mask an
interrupt by clearing the corresponding bit in the CIMR and you can enable one by setting
the corresponding bit in the CIMR. When a masked CPM interrupt occurs, the corresponding
bit in the CIPR is still set, regardless of the CIMR bit, but no interrupt request is passed to
the core.
If a CPM interrupt source is requesting interrupt service when you clear its corresponding
bit in the CIMR, the request stops. If you set its bit in the CIMR later, a previously pending
interrupt request is processed by the core, according to its assigned priority. You can read
the CIMR at any time and it is cleared by reset.
CIMR
BIT 0 1 2
FIELD
PC15 USB SCC2
RESET
0 0 0
R/W
R/W R/W R/W
ADDR
BIT 16 17 18
FIELD
PC11 PC10 RES
RESET
0 0 0
R/W
R/W R/W R/W
ADDR
16-509
3 4 5 6 7
TIMER
SCC3 RES PC14 PC13
1
0 0 0 0 0
R/W R/W R/W R/W R/W
(IMMR & 0xFFFF0000) + 0x948
19 20 21 22 23
TIMER
PC9 PC8 PC7 RES
3
0 0 0 0 0
R/W R/W R/W R/W R/W
(IMMR & 0xFFFF0000) + 0x94A
MPC823e REFERENCE MANUAL
8 9 10 11 12
PC12 SDMA IDMA1 IDMA2 RES
0 0 0 0 0
R/W R/W R/W R/W R/W
24 25 26 27 28
TIMER
PC6 SPI SMC1 SMC2
4
0 0 0 0 0
R/W R/W R/W R/W R/W
13 14 15
TIMER
R–TT I2C
2
0 0 0
R/W R/W R/W
29 30 31
PC5 PC4 RES
0 0 0
R/W R/W R/W
MOTOROLA