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This field is compared to the address on the address bus to determine if a PCMCIA window
is being accessed by an internal bus master. These bits are used in conjunction with the
BSIZE field in the POR.
17.5.6 PCMCIA Option Registers
The PCMCIA option registers 0-7 (POR0-POR7) control the size, timing parameters, and
memory access to the individual PCMCIA windows whose base addresses reside in the
corresponding PCMCIA base registers.
POR0–POR7
BIT
0
1
2
FIELD
BSIZE
RESET
—
R/W
R/W
(IMMR & 0xFFFF0000) + 0x84 (POR0), 0x8C (POR1), 0x94 (POR2), 0x9C (POR3),
ADDR
BIT
16
17
18
FIELD
PSST
RESET
—
R/W
R/W
(IMMR & 0xFFFF0000) + 0x84 (POR0), 0x8C (POR1), 0x94 (POR2), 0x9C (POR3),
ADDR
NOTE: — = Undefined.
BSIZE—PCMCIA Bank Size
This field determines the bank size (the size of the address space in bytes) for the
corresponding PCMCIA window. The bank size is also used as an address mask and is
applied to the PBA field in the associated PCMCIA base register to an address generated
by an internal master. The bank size is calculated from BSIZE as:
GRAYCODE BSIZE
BankSize
=
2
00000 = 1 bytes.
00001 = 2 bytes.
00011 = 4 bytes.
00010 = 8 bytes.
00110 = 16 bytes.
00111 = 32 bytes.
MOTOROLA
3
4
5
6
7
RESERVED
R/W
0xA4 (POR4), 0xAC (POR5), 0xB4 (POR6), 0xBC (POR7)
19
20
21
22
23
PSL
—
R/W
0xA4 (POR4), 0xAC (POR5), 0xB4 (POR6), 0xBC (POR7)
(
)
MPC823e REFERENCE MANUAL
PCMCIA Interface
8
9
10
11
12
—
24
25
26
27
28
PSL
PPS
PRS
—
—
R/W
R/W
R/W
13
14
15
PSHT
—
R/W
29
30
31
WP
PV
OT
—
—
—
R/W
R/W
17-17
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