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MPC823e Instruction Set—eciwx
B-54
EA must be a multiple of four. If it is not, one of the following
occurs:
•
A system alignment exception is generated.
•
A DSI exception is generated (possible only if EAR[E] = 0).
•
The results are boundedly undefined.
The eciwx instruction is supported for EAs that reference
memory segments in which SR[T] = 1 and for EAs mapped by
the DBAT registers. If the EA references a direct-store segment
(SR[T] = 1), either a DSI exception occurs or the results are
boundedly undefined. However, note that the direct-store facility
is being phased out of the architecture and will not likely be
supported in future devices. Thus, software must not depend on
its effects.
If this instruction is executed when MSR[DR] = 0 (real
addressing mode), the results are boundedly undefined. This
instruction is treated as a load from the addressed byte with
respect to address translation, memory protection, referenced
and changed bit recording, and the ordering performed by eieio.
This instruction is optional in the PowerPC architecture.
Other registers altered:
•
None
POWERPC ARCHITECTURE
LEVEL
VEA
MPC823e REFERENCE MANUAL
SUPERVISOR
OPTIONAL
LEVEL
√
MOTOROLA
FORM
X
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