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Video Controller
VIDEO
CLOCK
HSYNC
VD0-VD7
(YC
C
)
r
b
VD0-VD7
(RGB)
19.2.2 FIFO and DMA Control
The video controller FIFO consists of 24 32-bit entries. The DMA control block handles all
data transfers to the FIFOs and keeps them filled. At the appropriate time, each FIFO is filled
by the DMA control block in 16-byte transfers. The frame buffer address must be 16-byte
aligned. When the video controller is enabled, video data transfers to the panel start after
five DMA burst accesses have filled the FIFOs. See Section 16.5.1 SDMA Bus Arbitration
and Transfers for the proper arbitration configuration between the video controller DMA
and SDMA. The FIFO has two sets of control registers (0 and 1) associated with the video
RAM arrays (RAM_0 or RAM_1 appropriately). If there are problems with the screen
blanking when your caches are on, set the SDCR to 0x40.
The DMA control supports both interlace and noninterlace (progressive) scanning schemes.
In interlace mode, the DMA fetches the video components of odd lines from display frame
buffer A followed by the even lines from display frame buffer B. In noninterlace mode, the
lines are fetched sequentially from buffer A. No matter which mode you use, the video
components of a line must be stored in an integer number of bursts.
If the FIFO underruns during a frame, the video controller forces background video on the
screen until synchronization between the FIFO and video control RAM array is regained.
Synchronization means the FIFO and the video control RAM array are ready to display a
frame from its beginning. At that point, the video controller starts reprocessing the frame at
the beginning of the video control RAM array.
19.2.3 Image Sizes
The video controller can be used to display an image that is smaller than the size of the
display. The area that is used to display the image is defined as the "active display area" and
its video components are taken from the frame buffer. The inactive area is driven with a
single user-programmable default background color. The video controller changes smoothly
between two image sizes without disturbing the video timings. A display format is defined by
the pattern in the RAM array (set RAM_0 or RAM_1) and the appropriate FIFO control
register set (set_0 or set_1). The active RAM set contains the pattern associated with the
currently displayed image and the other RAM set contains the pattern associated with the
second image.
19-4
Y
C
Y
C
r
b
B
R
G
B
Figure 19-3. Output Timing Example
MPC823e REFERENCE MANUAL
C
Y
C
b
r
R
G
B
MOTOROLA
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