Motorola MPC823e Reference Manual page 1059

Figure 19-8 illustrates the horizontal timing of a single horizontal line that is represented by
five RAM entries:
• A defines the section of the line where the both the BLANK and HSYNC signals are
asserted.
• B defines the section of the line where the HSYNC signal is negated and BLANK is
asserted.
• C defines the section of the line where the HSYNC and BLANK signals are negated
while the driven data is background.
• D defines the section of the line where the HSYNC and BLANK signals are negated
while the driven data is the image data.
• E defines the section of the line where the BLANK signal is asserted and HSYNC is
negated.
A
LINE 3
HSYNC
FIELD
BLANK
128 PIXELS
(256 CLOCKS)
4 PIXELS
(8 CLOCKS)
MOTOROLA
B C D
LINE 4
720 PIXELS
(1440 CLOCKS)
864 PIXELS
(1728 CLOCKS)
Figure 19-8. PAL Horizontal Timing
MPC823e REFERENCE MANUAL
Video Controller
E
12 PIXELS
(24 CLOCKS)
19-25