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dcbz
Assembler Syntax
BIT
0
1
2
FIELD
31
BIT
16
17
18
FIELD
B
Definition
Operation
Description
MOTOROLA
dcbz
rA,rB
3
4
5
6
7
00000
19
20
21
22
23
Data Cache Block Set to Zero
EA is the sum ( r A|0) + ( r B).
The dcbz instruction executes as follows:
If the cache block containing the byte addressed by EA is
in the data cache, all bytes are cleared.
If the cache block containing the byte addressed by EA is
not in the data cache and the corresponding page is
caching-allowed, the cache block is allocated in the data
cache (without fetching the block from main memory),
and all bytes are cleared.
If the page containing the byte addressed by EA is in
caching-inhibited or write-through mode, either all bytes
of main memory that correspond to the addressed cache
block are cleared or the alignment exception handler is
invoked. The exception handler clears all bytes in main
memory that corresponds to the addressed cache block.
If the cache block containing the byte addressed by EA is
in coherency-required mode, and the cache block exists
in the data cache(s) of any other processor(s), it is kept
coherent in those caches.
MPC823e REFERENCE MANUAL
MPC823e Instruction Set—dcbz
8
9
10
11
12
24
25
26
27
28
1014
13
14
15
A
29
30
31
0
B-47
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