Motorola MPC823e Reference Manual page 464

Communication Processor Module
CPCR
BIT 0 1 2
FIELD RST RESERVED
RESET 0 0
R/W R/W R/W
ADDR
RST—Software Reset Command
This bit is set by the core and cleared by the communication processor module and when
this command is executed, the RST and FLG bits are cleared within two general system
clocks. The RISC reset routine is approximately 60 clocks long, but you can start initializing
the communication processor module immediately after this command is issued. RST is
useful when the core wants to reset the registers and parameters for all the channels as well
as the RISC microprocessor and timer tables. However, this bit does not affect the serial
interface or parallel I/O registers.
0 = No reset is issued.
1 = Reset is issued.
Bits 1–3—Reserved
These bits are reserved and must be set to 0.
OPCODE—Operation Code
This field is used in conjunction with the CH_NUM field to define a command sent to the
CPM. It issues a variety of commands, which are described in Table 16-2. For the same
operation code, the results may be different, depending on the channel number you select.
For example, if your operation code is 0101 ( GRACEFUL STOP TX ) and your channel
number is set to 0100 (SCC2), then the operation will gracefully stop the transmit on SCC2.
If your channel number is set to 0001 (IDMA1), then the operation will gracefully stop the
transmit on IDMA1.
CH_NUM—Channel Number
This field is set by the core to define the peripheral I/O channel that the command is applied
to. Some peripherals share channel number encodings if their commands are mutually
exclusive. See Table 16-2 for more information.
Bits 12–14—Reserved
These bits are reserved and must be set to 0.
16-10
3 4 5 6 7
OPCODE
0
R/W
(IMMR & 0xFFFF0000) + 0x9C0
MPC823e REFERENCE MANUAL
8 9 10 11 12
CH_NUM RESERVED
0
R/W
13 14 15
FLG
0 0
R/W R/W
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