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DIW2EN—Development Port Instruction Watchpoint Trap Enable 2
This is a read-only bit.
0 = Trap disabled (reset value).
1 = Trap enabled.
DIW3EN—Development Port Instruction Watchpoint Trap Enable 3
This is a read-only bit.
0 = Trap disabled (reset value).
1 = Trap enabled.
IFM—Ignore First Match Only for Instruction Breakpoints
0 = Do not ignore first match. Used for "Go To x" (reset value).
1 = Ignore first match. Used for "Continue".
ISCT_SER—Instruction Fetch Show Cycle and Core Serialize Control
This field defines one of several performance versus visibility options for core behavior. 111
is the preferred encoding for normal operation. Changing the instruction show cycle
programming starts to take effect only from the second instruction after the actual mtspr
instruction to ICTRL.
000 = Core is fully serialized and show cycle will be performed for all fetched
instructions (reset value). Has a reset value of 0x00000000.
001 = Core is fully serialized and show cycle will be performed for all changes in the
program flow.
010 = Core is fully serialized and show cycle will be performed for all indirect changes
in the program flow.
011 = Core is fully serialized and no show cycles will be performed for fetched
instructions.
100 = Illegal.
101 = Core is not serialized (normal mode) and show cycle will be performed for all
changes in the program flow. If the fetch of the target of a direct branch is aborted
by the core, the target is not always visible on the external pins. This does not
affect program trace.
110 = Core is not serialized (normal mode) and show cycle will be performed for all
indirect changes in the program flow.
111 = Core is not serialized (normal mode) and no show cycles will be performed for
fetched instructions.
For more information, see Section 20.2.2 Controlling Instruction Fetch Show Cycles.
MOTOROLA
Development Capabilities and Interface
MPC823e REFERENCE MANUAL
20-47
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