Motorola MPC823e Reference Manual page 918

Communication Processor Module
• RFCR and TFCR—The RX and TX function code entries contain the value that you
want to appear on the AT pins when the associated SDMA channel accesses memory.
This register controls the byte-ordering convention used in the transfers.
RFCR
BIT 0 1
FIELD RESERVED
RESET 0
R/W R/W
ADDR
Bits 0–2—Reserved
These bits are reserved and must be set to 0.
BO—Byte Ordering
You must set these bits to select the required byte ordering of the data buffer.
00 = The DEC/Intel convention is used for byte ordering (swapped operation) and
is also called little-endian byte ordering. The transmission order of bytes within
a buffer word is reversed in comparison to the Motorola mode. This mode is
supported only for 32-bit port size memory.
01 = PowerPC little-endian byte ordering. As data is transmitted onto the serial line
from the data buffer, the least-significant byte of the buffer double-word
contains data to be transmitted earlier than the most-significant byte of the
same buffer double-word.
1X = Motorola byte ordering (normal operation) is also called big-endian byte
ordering. As data is transmitted onto the serial line from the data buffer, the
most-significant byte of the buffer word contains data to be transmitted earlier
than the least-significant byte of the same buffer word.
AT—Address Type 1–3
These bits contain the function code value used during the SDMA channel memory
access. AT0 is driven with a 1 to identify this SDMA channel access as a DMA-type
access.
TFCR
BIT 0 1
FIELD RESERVED
RESET 0
R/W R/W
ADDR
16-464
2 3 4
BO
0
R/W
I2C BASE + 0x04
2 3 4
BO
0
R/W
I2C BASE + 0x05
MPC823e REFERENCE MANUAL
5 6 7
AT
0
R/W
5 6 7
AT
0
R/W
MOTOROLA