Table of Contents
Advertisement
MPC823e Instruction Set—sraw
sraw
Assembler Syntax
BIT
0
1
2
FIELD
31
BIT
16
17
18
FIELD
B
Definition
Operation
Description
B-124
sraw
rA,rS,rB (Rc = 0)
sraw.
rA,rS,rB (Rc = 1)
3
4
5
6
7
19
20
21
22
23
Shift Right Algebraic Word
← rB[27-31]
n
rA ← ROTL(rS,
)
n
If rB[26] = 0,then the contents of rS are shifted right the number
of bits specified by rB[27–31]. Bits shifted out of position 31 are
lost. The result is padded on the left with sign bits before being
placed into rA. If rB[26] = 1, then rA is filled with 32 sign bits (bit
0) from rS. CR0 is set based on the value written into rA.
XER[CA] is set if rS contains a negative number and any 1 bits
are shifted out of position 31; otherwise XER[CA] is cleared. A
shift amount of zero causes XER[CA] to be cleared.
The sraw instruction, followed by addze, can by used to divide
n
quickly by 2
. The setting of the XER[CA] bit, by sraw, is
independent of mode.
Other registers altered:
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO(if Rc = 1)
XER:
Affected: CA
MPC823e REFERENCE MANUAL
8
9
10
11
12
S
24
25
26
27
28
792
13
14
15
A
29
30
31
RC
MOTOROLA
Advertisement
Table of Contents
