Motorola MPC823e Reference Manual page 1084

Figure 20-6 illustrates the debug mode logic implemented in the core.
INTERRUPT CAUSE REGISTER (ICR)
DEBUG ENABLE REGISTER (DER)
RFI
RESET
DEBUG MODE ENABLE
Figure 20-6. Debug Mode Logic Implementation
MOTOROLA
Development Capabilities and Interface
DECODER
SET
Q
INTERNAL DEBUG
MODE SIGNAL
MPC823e REFERENCE MANUAL
EVENT (CORE INTERRUPT
5 OR EXCEPTION)
EVENT VALID
FREEZE
ICR_OR
20-23