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MPC823e Instruction Set—lhzux
lhzux
Assembler Syntax
BIT
0
1
2
FIELD
31
BIT
16
17
18
FIELD
B
Definition
Operation
Description
B-76
lhzux
rD,rA,rB
3
4
5
6
7
19
20
21
22
23
Load Half Word and Zero with Update Indexed
EA ← (rA) + (rB)
rD ← (16)0 || MEM(EA, 2)
rA ← EA
EA is the sum (rA) + (rB). The half word in memory addressed
by EA is loaded into the low-order 16 bits of rD. The remaining
bits in rD are cleared. EA is placed into rA. If rA = 0 or rA = rD,
the instruction form is invalid.
Other registers altered:
None
POWERPC ARCHITECTURE
LEVEL
UISA
MPC823e REFERENCE MANUAL
8
9
10
11
12
D
24
25
26
27
28
311
SUPERVISOR
OPTIONAL
LEVEL
13
14
15
A
29
30
31
0
FORM
X
MOTOROLA
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