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Communication Processor Module
16.9.21.4.1 Inline Synchronization Pattern. The transparent channel can be
programmed to transmit and receive a synchronization pattern if the SYNL field in the
GSMR_H are not zero. This pattern is defined in the data synchronization register and the
length of the Sync pattern is defined in the SYNL field. If the SYNL field is 00, then the DSR
is not used and an external Sync signal is used instead. See Section 16.9.4 Data
Synchronization Register and Section 16.9.2 The General SCCx Mode Registers for
more information.
DSR–SCC TRANSPARENT (SYNL = 01)
BIT
0
1
2
FIELD
4-BIT SYNC
RESET
0
1
1
R/W
R/W
ADDR
NOTE: X = "Don't Care".
DSR–SCC TRANSPARENT (SYNL = 10)
BIT
0
1
2
FIELD
RESET
0
1
1
R/W
ADDR
NOTE: X = "Don't Care".
DSR–SCC TRANSPARENT (SYNL = 11)
BIT
0
1
2
FIELD
RESET
0
1
1
R/W
ADDR
16-304
3
4
5
6
1
1
1
1
(IMMR & 0xFFFF0000) + 0xA2E
3
4
5
6
8-BIT SYNC
1
1
1
1
R/W
(IMMR & 0xFFFF0000) + 0xA2E
3
4
5
6
16-BIT SYNC
1
1
1
1
(IMMR & 0xFFFF0000) + 0xA2E
MPC823e REFERENCE MANUAL
7
8
9
10
11
X
0
0
1
1
1
R/W
7
8
9
10
11
0
0
1
1
1
7
8
9
10
11
0
0
1
1
1
R/W
12
13
14
15
1
1
1
0
12
13
14
15
X
1
1
1
0
R/W
12
13
14
15
1
1
1
0
MOTOROLA
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