Motorola MPC823e Reference Manual page 926

Communication Processor Module
W—Wrap (Final Buffer Descriptor in Table)
0 = This is not the last buffer descriptor in the TX buffer descriptor table.
1 = This is the last buffer descriptor in the TX buffer descriptor table. After this buffer is
used, the communication processor module receives incoming data into the first
buffer descriptor that TBASE points to in the table. The number of TX buffer
descriptors in this table is programmable and determined only by the W bit and
overall space constraints of the dual-port RAM.
I—Interrupt
0 = No interrupt is generated after this buffer is serviced.
1 = The TXB or TXE bit in the I
and TXE can cause interrupts if they are enabled.
L—Last
0 = This buffer does not contain the last character of the message.
1 = This buffer contains the last character of the message.
S—Transmit Start Condition
When this bit is set to 1, the I
the buffer. If this buffer descriptor is the first one in the frame, a start condition is transmitted,
regardless of the value of this bit. This bit provides the ability to transmit a start byte or
back-to-back frames.
0 = A start condition is not transmitted before the first byte of the buffer, unless it is the
first byte of a frame.
1 = A start condition is transmitted before the first byte of the buffer.
NAK—No Acknowledge
This bit indicates that the transmission has been aborted because the last transmitted byte
was not acknowledged. The I
associated data buffer.
UN—Underrun
This bit indicates that the I
while transmitting the associated data buffer. The I
transmitting the associated data buffer.
CL—Collision
This bit indicates that transmission has been aborted because the transmitter was lost while
arbitrating for the bus. The I
associated data buffer.
16-472
2
C event register is set when this buffer is serviced. TXB
2
C controller transmits a start condition before the first byte of
2
C controller writes this bit after it finishes transmitting the
2
C controller has encountered a transmitter underrun condition
2
C controller writes this bit after it finishes
2
C controller writes this bit after it finishes transmitting the
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