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MPC823e Instruction Set—lhau
lhau
Assembler Syntax
BIT
0
1
2
FIELD
43
BIT
16
17
18
FIELD
Definition
Operation
Description
B-70
lhau
rD,d(rA)
3
4
5
6
7
19
20
21
22
23
d
Load Half Word Algebraic with Update
EA ← (rA) + EXTS(d)
rD ← EXTS(MEM(EA, 2))
rA ← EA
EA is the sum (rA) + d. The half word in memory addressed by
EA is loaded into the low-order 16 bits of rD. The remaining bits
in rD are filled with a copy of the most-significant bit of the loaded
half word. EA is placed into rA. If rA = 0 or rA = rD, the instruction
form is invalid.
Other registers altered:
None
POWERPC ARCHITECTURE
LEVEL
UISA
MPC823e REFERENCE MANUAL
8
9
10
11
12
D
24
25
26
27
28
SUPERVISOR
OPTIONAL
LEVEL
13
14
15
A
29
30
31
FORM
D
MOTOROLA
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