Motorola MPC823e Reference Manual page 649

The DPLL has a carrier-sense signal that indicates when there are data transfers on the
RXDx signal. Using the TSNC field of the GSMR_L, this signal is asserted as soon as a
transition is detected on RXDx and it is negated after a programmable number of clocks
have been detected with no transitions.
To prevent itself from locking on the wrong edges and to provide fast synchronization, the
DPLL must receive a preamble pattern before it receives the data. In some protocols, the
preceding flags or syncs are used. However, some protocols require a special pattern, such
as alternating ones and zeros. When a transmission occurs, a serial communication
controller can generate preamble patterns as programmed in the TPP and TPL bits of the
GSMR_L.
Table 16-25. Preamble Patterns for Decoding Methods
DECODING METHOD
NRZI Mark
NRZI Space
FM0
FM1
Manchester
Differential Manchester
In addition, the DPLL can be used to invert the datastream of a reception or transmission.
This feature is available in all encodings, including the standard NRZ data format. Also,
when the transmitter is idle, the DPLL can either force the TXDx signal to a high voltage or
continue encoding the data supplied to it. The DPLL is used for UART encoding/decoding,
which gives you the option of selecting the divide ratio in the UART decoding process (8x,
16x, or 32x). Typically, 16x option is used.
The maximum data rate that can be supported with the DPLL is 3.125MHz when operating
with a 25MHz system clock, assuming that the 8× option is chosen
(25MHz ÷ 8 = 3.125MHz). Thus, the frequency applied to the CLKx pin or generated by an
internal baud rate generator may be up to 25MHz on a 25MHz MPC823e, if the DPLL 8x,
16x, or 32x options are used.
Note: The 1:2 ratio of GCLK1 to the serial clock does not apply when the DPLL is used
to recover the clock in the 8x, 16x, or 32x modes. Synchronization occurs
internally after the receive clock is generated by the DPLL. Therefore, even the
fastest DPLL clock generation (the 8x option) easily meets the required 1:2 ratio
clocking limit.
MOTOROLA
PREAMBLE PATTERN
All zeros
All ones
All ones
All zeros
Repeating 10's
All ones
MPC823e REFERENCE MANUAL
Communication Processor Module
MAXIMUM PREAMBLE
LENGTH REQUIRED
8-bit
8-bit
8-bit
8-bit
8-bit
8-bit
16-195