Motorola MPC823e Reference Manual page 1018

18.4 REGISTER MODEL
18.4.1 LCD Controller Configuration Register
The 32-bit, memory mapped, read/write LCD controller configuration register (LCCR) holds
the mode and configuration parameters that you can use to operate your LCD panel.
LCCR
BIT 0 1 2
FIELD
RESET
R/W
ADDR
BIT 16 17 18
FIELD
IEN IRQL
RESET 0 0
R/W
R/W R/W
ADDR
BNUM—Number of Bursts
This field contains the number of burst cycles required for one refresh cycle.
EIEN—Exception Interrupt Enable
0 = The underrun or bus error interrupt is disabled.
1 = The underrun or bus error interrupt is enabled.
IEN—Interrupt Enable
0 = The end-of-frame interrupt is disabled.
1 = The end-of-frame interrupt is enabled.
IRQL—Interrupt Request Level
This field contains the priority request level of the LCD controller's interrupt that is sent to
the system interface unit. Refer to Section 12.3.3 Programming the Interrupt Controller
for more information. This will generate an interrupt request level with a vector in the SIVEC
register if enabled with the SIMASK register. Both EOF and the exception interrupts use the
same request level.
CLKP—Clock Polarity
0 = The SHIFT/CLK pin polarity is active high.
1 = The SHIFT/CLK pin polarity is active low.
MOTOROLA
3 4 5 6 7
BNUM
0
R/W
(IMMR & 0xFFFF0000) + 0x840
19 20 21 22 23
CLKP OEP HSP VSP
0 0 0 0
R/W R/W R/W R/W R/W
(IMMR & 0xFFFF0000) + 0x842
MPC823e REFERENCE MANUAL
8 9 10 11 12
24 25 26 27 28
DP BPIX LBW SPLT CLOR
0 0 0 0
R/W R/W R/W
LCD Controller
13 14 15
EIEN
0
R/W
29 30 31
TFT PON
0 0 0
R/W R/W R/W
18-21