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mulhwu
Assembler Syntax
BIT
0
1
2
FIELD
31
BIT
16
17
18
FIELD
B
Definition
Operation
Description
MOTOROLA
mulhwu
rD,rA,rB(Rc = 0)
mulhwu.
rD,rA,rB(Rc = 1)
3
4
5
6
7
19
20
21
22
23
0
Multiply High Word Unsigned
prod[0–63] ← rA ∗ rB
rD ← prod[0–31]
The 32-bit operands are the contents of rA and rB. The high
order 32 bits of the 64-bit product of the operands are placed into
rD. Both the operands and the product are interpreted as
unsigned integers, except that if Rc = 1 the first three bits of CR0
field are set by signed comparison of the result to zero. This
instruction may execute faster on some implementations if rB
contains the operand having the smaller absolute value.
Other registers altered:
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO (if Rc = 1)
POWERPC ARCHITECTURE
LEVEL
UISA
MPC823e REFERENCE MANUAL
MPC823e Instruction Set—mulhwu
8
9
10
11
12
D
24
25
26
27
28
11
SUPERVISOR
OPTIONAL
LEVEL
13
14
15
A
29
30
31
RC
FORM
XO
B-105
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