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Development Capabilities and Interface
Table 20-11. Debug Instructions/Data Shifted Into the DPS Register
START
MODE
CONTROL
1
0
0
1
0
1
1
1
0
1
1
1
1
1
1
NOTE: See Table 20-8 for details on trap enable bits and Table 20-9 for details on debug port commands.
All transmissions from the debug port on DSDO begin with a zero or ready bit. This indicates
that the core is trying to read an instruction or data from the port. The external development
tool waits until it sees DSDO go low before it starts sending the next transmission. The
control bit differentiates between instructions and data that allow the development interface
port to detect an instruction that was entered when the core was expecting data and vice
versa. If this occurs, a sequence error indication is shifted out in the next serial transmission.
The trap enable function allows the development interface port to transfer data to the trap
enable control register. The DEBUG PORT command allows the development tool to either
negate breakpoint requests, reset the processor, or activate or deactivate the fast download
procedure. The NOP function provides a null operation to use when there is data or a
response to be shifted out of the data register. The next appropriate instruction or command
will be determined by the value of the response or data shifted out.
The encoding of data shifted out of the development interface port shift register in debug
mode is the same for trap enable mode, as shown in Table 20-10. The valid data encoding
is used when data has been transferred from the core to the development interface port shift
register. This results when an instruction to move the contents of a general-purpose register
to the DPDR occurs. The valid data encoding has the highest priority of all status outputs
and will be reported even if an interrupt occurs at the same time. Since it is not possible for
a sequencing error to occur that has valid data, there is no priority conflict with the
sequencing error status. Also, any interrupt that is recognized at the same time that there is
valid data, is not related to the execution of an instruction. Therefore, a valid data status will
be output and the interrupt status will be saved for the next transmission.
20-38
INSTRUCTION / DATA (32 BITS)
BITS 0:6
BITS 7:31
CPU Instruction
CPU Data
Trap Enable
Not Exist
Bits
0011111
Not Exist
0
Not Exist
MPC823e REFERENCE MANUAL
FUNCTION
Transfer Instruction to Core
Transfer Data to Core
Transfer Data to Trap Enable
Control Register
Negate Breakpoint Requests
to Core
NOP
MOTOROLA
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