Motorola MPC823e Reference Manual page 432

Memory Controller
An asynchronous example interconnection in which an external master and the MPC823e
can both share access to a DRAM bank is illustrated in Figure 15-39. Notice that CS1,
UPMA, and GPL_A5 were chosen to assist in the control of DRAM bank accesses.
Figure 15-40 illustrates the timing behavior of the GPL_A5 and other control signals when
an external master to a DRAM bank initiates a single beat read access. The state of the
GPL_A5 pin in the first clock cycle of the memory device access is determined by the value
of the G5LS bit in the corresponding option register.
CS1
BSx
GPL_A5
Figure 15-39. Asynchronous External Master Interconnect Example
15-74
DRAM
MULTIPLEXER
A[6:31]
D[0:31]
R/W
AS
TSIZx
TA
BB
BR
BG
MPC823e REFERENCE MANUAL
EXTERNAL
MASTER
ARBITRATION
SIGNALS
EXTERNAL
ARBITER
MOTOROLA