Table of Contents
Advertisement
andis.
Assembler Syntax
BIT
0
1
2
FIELD
29
BIT
16
17
18
FIELD
Definition
Operation
Description
MOTOROLA
andis.
rA,rS,UIMM
3
4
5
6
7
19
20
21
22
23
UIMM
AND Immediate Shifted
rA ← (rS) + (UIMM || (16)0)
The contents of rS are ANDed with UIMM || 0x0000 and the
result is placed into rA.
Other registers altered:
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO
POWERPC ARCHITECTURE
LEVEL
UISA
MPC823e REFERENCE MANUAL
MPC823e Instruction Set—andis.
8
9
10
11
12
S
24
25
26
27
28
SUPERVISOR
OPTIONAL
LEVEL
13
14
15
A
29
30
31
FORM
D
B-19
Advertisement
Table of Contents
