Motorola MPC823e Reference Manual page 1328

Index
DSP programming for core,
external bus master,
general circuit interface,
half-word working mode 1,
half-word working mode 2,
HDLC bus controller programming,
HDLC interrupt event,
hierarchical bus interface,
16-149
IDL interface.
initializing the RISC timers,
interrupt table handling,
memory system interface
page mode extended data-out,
page-mode DRAM,
memory system interface,
17-22
PCMCIA timing,
port A configuration,
port B configuration,
RISC timer interrupt handling,
SCC2 in AppleTalk mode programming,
SCC2 in Ethernet mode programming,
SCC2 in high-speed IrDA mode programming,
16-300
SCC2 in low-speed IrDA mode programming,
16-297
SCC2 in middle-speed mode programming,
298
SCC2 in Transparent mode programming,
317
SCCx HDLC receive buffer descriptor,
SCCx in ASYNC HDLC mode programming,
286
SCCx in Ethernet mode receive buffer
16-340
descriptor,
SCCx in HDLC mode address recognition,
238
SCCx in HDLC mode programming,
16-256
SCCx in UART mode programming,
SCCx in UART mode S-record programming,
16-232
SCCx UART interrupt event,
SCCx UART receive buffer descriptor,
serial peripheral interface master programming,
16-453
serial peripheral interface slave programming,
16-454
slow device interface,
SMC in Transparent mode programming NMSI,
16-423
SMC in Transparent mode TSA programming,
16-424
SMC in UART mode programming,
SMC in UART mode receive buffer descriptor,
16-402
Index-10
16-36
15-72
16-153
20-13
20-14
16-264
16-251
15-67
16-24
12-11
15-88
15-76
15-76
16-482
16-490
16-25
16-269
16-348
16-
16-
16-245
16-
16-
16-255
,
16-230
16-227
16-221
15-67
16-407
MPC823e REFERENCE MANUAL
SPI with different LEN values,
16-81
timer initialization,
11-50
translation reload,
transparent synchronization,
16-162
UART baud rate,
universal serial bus initialization,
380
video controller programming,
examples, instruction execution,
exception control cycles,
15-59
exception handling,
6-7
exception sources,
6-7
exception, causes of,
exception, detecting an,
20-28
exceptions,
7-2
exceptions, PowerPC,
16-73
execution, DSP,
exiting from low-power mode,
15-41
EXS (definition),
2-6
EXTAL,
2-6
EXTCLK,
external accesses (definition),
15-68
external bus masters,
external bus, operating at lower frequencies,
4-3
external hard reset,
external interrupt
6-13
latency,
external memory access requests,
4-4
external soft reset,
F
features
baud rate generators,
14-5
big endian mode,
13-1
bus interface,
clocks and power control,
communication processor module,
6-1
core,
CPM interrupt controller,
10-1
data cache,
development capabilities,
digital signal processing,
HDLC bus controller,
16-457
I2C controller,
16-90
IDMA,
9-1
instruction cache,
18-1
LCD controller,
14-3
little endian mode,
15-1
memory controller,
memory management unit,
not supported by SMC in UART mode,
16-478
parallel I/O ports,
17-1
PCMCIA,
PowerPC little-endian mode,
16-445
16-306
16-378 16-
,
19-19
8-4
13-41
6-9
5-28
15-68
5-17
15-42
16-157
5-1
16-1
16-501
20-1
16-26
16-259
11-1
16-392
14-5
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