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lwarx
Assembly Syntax
BIT
0
1
2
FIELD
31
BIT
16
17
18
FIELD
B
Definition
Operation
Description
MOTOROLA
lwarx
rD,rA,rB
3
4
5
6
7
19
20
21
22
23
Load Word and Reserve Indexed
if rA = 0 then b ← 0
else b ← (rA)
EA ← b + (rB)
RESERVE ← 1
RESERVE_ADDR ← physical_addr(EA)
rD ← MEM(EA,4)
EA is the sum (rA|0) + (rB). The word in memory addressed by
EA is loaded into rD.
This instruction creates a reservation for use by a store word
conditional indexed (stwcx.) instruction. The physical address
computed from EA is associated with the reservation, and
replaces any address previously associated with the reservation.
EA must be a multiple of four. If it is not, either the system
alignment exception handler is invoked or the results are
boundedly undefined. When the RESERVE bit is set, the
processor enables hardware snooping for the block of memory
addressed by the RESERVE address.
If the processor detects that another processor writes to the
block of memory it has reserved, it clears the RESERVE bit. The
stwcx. instruction will only do a store if the RESERVE bit is set.
The stwcx. instruction sets the CR0[EQ] bit if the store was
successful and clears it if it failed. The lwarx and stwcx.
combination can be used for atomic read-modify-write
sequences.
MPC823e REFERENCE MANUAL
MPC823e Instruction Set—lwarx
8
9
10
11
12
D
24
25
26
27
28
20
13
14
15
A
29
30
31
0
B-83
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