Motorola MPC823e Reference Manual page 1351

16-80
TCNx,
16-80
TCRx,
2-12
TDI,
16-112
TDM (definition),
16-117
TDM channel routing,
2-12
TDO,
TEA assertion, not occurring,
2-3 13-6 13-36
TEA, , ,
20-31
TECR,
termination
16-265
LocalTalk frame,
termination control of a bus cycle error,
13-37
termination signals,
24-1
terminology,
16-81
TERx,
12-36
TESR,
test access port
21-1
21-2
block diagram,
boundary scan bit order,
boundary scan register,
instruction register,
instructions
21-20
bypass,
21-20
clamp,
21-19
extest,
21-20
hi-z,
sample/preload,
21-21
restrictions,
21-3
TAP controller,
2-7
TEXP,
2-10
TGATE1,
2-10
TGATE2,
16-77
TGCRx,
timebase and decrementer register key,
timebase reference register 0 key,
timebase reference register 1 key,
timebase reference registers,
timebase register mapping,
12-14
timebase register,
timebase status and control register key,
timebase status and control register,
12-14
timebase,
16-273
time-fill,
timer capture registers (TCRx),
timer counter registers (TCNx),
timer event registers (TERx),
timer global configuration register (TGCRx),
timer global configuration register,
timer mode registers (TMRx),
timer reference registers (TRRx),
timers
3-4
key memory map,
3-7
memory map,
16-74
timers,
MOTOROLA
15-16
13-42
21-6
21-4
21-19
21-20
5-27
5-27
5-27
12-15
6-16
5-27
12-16
16-80
16-80
16-81
16-77
16-76
16-78
16-79
MPC823e REFERENCE MANUAL
time-slot assigner
16-114
configuration,
16-117
connections,
16-114
features,
timing
bus arbitration (illustration),
16-189
SCCx,
timing, instruction cycles,
16-110
timing, single buffer,
2-8
TIN1,
2-9
TIN2,
2-8
TIN3,
2-9
TIN4,
TLB manipulation
loading the reserved TLB entries,
11-51
TLB invalidation,
TLB replacement counter,
11-15
tlbia,
11-15
tlbie,
16-78
TMRx,
2-12
TMS,
tokens
16-357
IN,
16-358
PRE,
16-357
SETUP,
16-358
SOF,
2-8
TOUT1,
2-9
TOUT2,
tracking microcontroller loading,
transfer error status register,
13-31
transfer start,
transfers on the bus
alignment and packaging,
13-8
basic,
13-16
burst,
read
13-26
bytes,
13-8
single beat,
write
13-27
patterns,
transfers, burst-inhibited,
translation table structure,
transparency decoding, receiver,
transparency encoding, transmitter,
Transparent mode
16-301
SCCx,
16-79
TRRx,
2-12
TRST,
2-2 13-5
TS,
,
16-112
TSA (definition),
13-33
TSIZ,
2-2
TSIZ0,
2-2
TSIZ1,
16-321
TXD,
2-8
TXD2,
Index
13-30
8-1
11-51
11-51
16-25
12-36
13-25
13-16
11-5
16-271
16-271
Index-33